1. Field of the Invention
The present invention relates to a vector data buffer device which is built into a vector data processor in order to store arrayed data items received from a storage area.
2. Description of the Related Art
Data transfer between a main storage and a buffer memory for storing a copy of the main storage data is usually performed in single-block units (where one block consists of, for example, 64 bytes), and the data is transferred between the same columns of the main store and the buffer memory.
The buffer memory also consists of a set of registers called an address array (index array or data directory), in which the numbers of blocks stored in the corresponding locations of the buffer memory are set. Since the blocks of consecutive numbers belong to different columns, the loads of the individual columns are ordinarily averaged. As a result, there is a 90% probability that a required block exists in the buffer memory.
However, in the case where the main storage area is divided into a plurality of modules, storage is accomplished by adopting a memory interleaving technique so that all the modules may operate in parallel, when dealing with consecutive addresses, to realize a data transfer rate a number-of-modules times faster.
In this regard, a recent storage controller has a plurality of instruction processors and input/output processors connected thereto in order to enhance the performance of the whole system, and the main storage area is provided with a large number of storing banks capable of operating independently of one another, in order to enhance the processing throughput thereof. In, for example, a vector computer, a plurality of processors are connected to one common main storage area, and the respective processors need to access the shared main storage and to fetch data at high speeds for the purpose of parallel processing.
Herein, in a case where the instruction processors numbers four, by way of example, and are connected to the main storage, this main storage is endowed with four ports in order to enhance the throughput thereof, and the respective ports operate independently of one another. From the viewpoint of one particular instruction processor, however, it is not at all certain that data items will be sent to the processor in the sequence of requests issued by that particular processor. More specifically, assuming that a particular processor has successively requested port-0 and port-1 to deliver data items, which of these ports will afford the data earlier is quite unknown. In the case where a vector computation or the like is allotted to and processed by the plurality of instruction processors, it forms an obstacle to the operation that data fetch sequences differ from the queues of arrayed data fetch requests issued by the instruction processors.
As an expedient method for storing such data items fetched from the storage area, in an operand buffer in the same sequence that the requests were issued, there has heretofore been, for example, a method disclosed in the official gazette of Japanese Patent Application Laid-open No. 60-136849. With the prior-art method, when the request is issued, information on the location of the buffer memory is affixed to this request, and when the data is fetched from the storage area and sent to the buffer memory, this information is also sent back, whereby the data is stored in the buffer memory on the basis of the location information.
In this method, however, logic corresponding to the number of the connected instruction processors need to be held on the storage side, so that the quantity of hardware increases significantly. More specifically, the information items relating to the locations of the buffer need to be carried about within the interval storage area in the number of the processors connected to the main storage. In recent storage systems, especially those having a large number of processors connected thereto, the quantity of hardware becomes enormous, thus rendering the method unfeasible.